Semiconductor memory devices are typically classified into volatile memory devices and non-volatile memory devices. Volatile memory devices are subdivided into dynamic random access memories (DRAMs) and static random access memories (SRAMs). Non-volatile memory types include mask read-only memories (MROMs), programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), and electrically erasable programmable read-only memories (EEPROMs). EEPROMs are increasingly used in system programming that requires continuous update or auxiliary memory devices. Particularly, flash EEPROMs are advantageous as mass storage devices because their integration density is high compared with conventional EEPROMs. Among the flash EEPROMs, a NAND-type flash EEPROM has a high integration density as compared with a NOR-type or AND-type flash EEPROM.
Currently, an operation in flash devices allows a user to copy data internally stored in one page (a page of memory is typically 256 bytes to 2 kilobytes in size) at a source address location to a destination address location directly, instead of writing out the data to an external memory and rewriting back to the destination. Thus, the operation is efficient since it only requires one step. This is one example of a copy-back operation. However, this type of copy-back is a blind operation. The user does not know if the correct data have been copied. If the data being copied are corrupted or otherwise incorrect, the data will be incorrectly written to the destination.
Thus, although this type of copy-back operation appears to increase the performance of the device, it does not ensure the reliability of data at the source. Consequently, this copy-back scheme does not prevent erroneous data from being copied to the destination address.
One of the predominant ways reliability can be ensured is by using an error correction code (ECC). Various error correction schemes may be employed to ensure the reliability of data memories. An error correction scheme can correct an error due to, for example, discharge loss, correct the integrity of the data and discard erroneous data. However for a typical error correction scheme to check data integrity, at least one additional serial random read cycle needs to be performed. The additional serial read step reduces performance of the flash device, and reduces entire system performance by tying up CPU buses and requiring CPU clock cycles to perform error correction.
FIG. 1 shows another copy-back scheme of the prior art. FIG. 1 includes a flash memory device 101, a microcontroller 107, and a serial bus 109. The flash memory device 101 contains a source address location 103 and a destination address location 105.
The flash memory device 101 may be, for example, a NAND-type device. The flash memory device 101 typically communicates with an external processing device such as the microcontroller 107 through the serial bus 109. The microcontroller 107 could also be another processing device such as a CPU or other microprocessor. To perform a copy-back operation, the microcontroller 107 first reads data contained at the source address location 103. The microcontroller 107 then writes a copy of the read data to the destination address location 105.
Finally, the microcontroller 107 verifies data written to the destination address location 105 by performing a final read operation (not shown) of the newly written data located at the destination address location 105. Although effective, typical copy-back schemes, such as shown in FIG. 1, are slow since all read and write operations between the flash memory device 101 and the microcontroller 107 must occur via the serial bus 109.
FIG. 2 shows another copy-back scheme of the prior art. In this scheme, an internal data register 209 is added to a flash memory device 201. Here, data stored at a source address location 203 are directly transferred to the data register 209. The data register 209 then transfers a copy of the data from what are stored in the source address location 203 to a destination address location 205. The system is capable of providing for a high-speed data transfer. However, there is no possibility of verifying data integrity since there is no interaction with the microcontroller 107. Typically, a microcontroller is required to perform error correction functions if necessary (e.g., such as executing an error correction code (ECC)). The presence of the data register 209 enables a caching operation so that data at the data register 209 can be modified by the microcontroller before it can be programmed at the destination address.
NAND-type flash EEPROM supports a page copy-back operation, which means data information can be copied from one page to another page without being output to an exterior. One such device is described in U.S. Pat. No. RE 36,732 to Miyamoto. The device disclosed is “a non-volatile semiconductor memory device for transferring data . . . without reading out read data to an external unit, when data is [sic] copied back” (emphasis added, Miyamoto Abstract). The Miyamoto device executes a copy-back operation by simultaneously copying memory data of one row to another row without using a CPU, thereby reducing a total copy-back time.
An additional memory device incorporating a copy-back operation is described in U.S. Patent Application Publication No. 2003/0076719 to Byeon et al. Byeon describes a “non-volatile memory device [which] . . . includes a page buffer acting as a sense amplifier during a read operation and as a write driver during a program operation. The page buffer has two sense and latch blocks, which exclusively carry out the same function. While one of the sense and latch blocks carries out a read operation, the other sense and latch block outputs previously sensed data to the exterior. Further, while one of the sense and latch blocks carries out a program operation, the other sense and latch block loads data to be programmed. Due to the page buffer, an operation speed of the non-volatile memory device can be enhanced” (emphasis added, Byeon Abstract).
However, neither Miyamoto nor Byeon et al. discloses a means to (1) verify data integrity; (2) perform error correction if data are invalid; or (3) simultaneously perform an external read operation while performing an internal programming operation.
Therefore, a system and method is needed for a flash memory device that can perform an external read operation while simultaneously performing an internal program operation, verify data integrity after a read operation and provide error correction if necessary.